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| geometry process details principal device types 2n6426 2n6427 cmpt6427 cmpta13 cmpta14 cxta14 czta14 mpsa13 mpsa14 mpsa27 gross die per 4 inch wafer 15,165 process cp307 small signal transistor npn - silicon darlington transistor chip process epitaxial planar die size 27 x 27 mils die thickness 9.0 mils base bonding pad area 5.3 x 3.8 mils emitter bonding pad area 5.3 x 6.5 mils top side metalization al - 30,000? back side metalization au - 18,000? backside collector www.centralsemi.com r6 (22-march 2010)
process cp307 typical electrical characteristics www.centralsemi.com r6 (22-march 2010) |
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